1. Field of the Invention
Generally, the subject matter disclosed herein relates to integrated circuits, and, more particularly, to N-channel and P-channel transistor devices. More particularly, the subject matter disclosed herein relates to improved MOSFETs with tuned work functions of the gate.
2. Description of the Related Art
Integrated circuits formed on semiconductor wafers typically include a large number of circuit elements, which form an electric circuit. In addition to active devices such as, for example, field effect transistors and/or bipolar transistors, integrated circuits can include passive devices such as resistors, inductors and/or capacitors. In particular, during the fabrication of complex integrated circuits using CMOS technology, millions of transistors, i.e., N-channel transistors and P-channel transistors, are formed on a substrate including a crystalline semiconductor layer.
A MOS transistor, for example, irrespective of whether an N-channel transistor or a P-channel transistor is considered, comprises so-called PN junctions that are formed by an interface of highly doped drain and source regions with an inversely or weakly doped channel region disposed between the drain region and the source region. The conductivity of the channel region, i.e., the drive current capability of the conductive channel, is controlled by a gate electrode formed near the channel region and separated therefrom by a thin insulating layer.
The conductivity of the channel region, upon formation of a conductive channel due to the application of an appropriate control voltage to the gate electrode, depends on, among other things, the dopant concentration, the mobility of the majority charge carriers and, for a given extension of the channel region in the transistor width direction, the distance between the source and drain regions, which is also referred to as channel length.
Hence, in combination with the capability of rapidly creating a conductive channel below the insulating layer upon application of the control voltage to the gate electrode, the overall conductivity of the channel region substantially determines the performance of the MOS transistors.
Polysilicon has been used as the MOSFET gate material for decades. However, as CMOS devices are scaled into the sub 50 nm regime, polysilicon gate technology issues such as gate depletion and boron penetration become more problematic. Furthermore, polysilicon has been reported to be incompatible with a number of high-k gate-dielectric candidates. For extremely scaled semiconductor devices, the conventional SiO2 gate insulator material begins to exhibit excessive leakage and, therefore, cannot reliably provide a sufficient electrical isolation between the gate electrode and the underlying channel region. Therefore, alternative materials having dielectric constants greater than about 4 (referred to herein as high-k dielectrics) have been considered for use in advanced devices including advanced CMOS devices. Gate insulators made from high-k dielectrics can be made thicker than those made of SiO2 without sacrificing capacity properties and thus offer the benefit of a significant reduction of leakage currents. Candidate materials include transitional metal oxides, silicates and oxynitrides, such as hafnium oxide, hafnium silicide and hafnium oxynitride.
As an example of the art, the manufacturing of a fully depleted field effect transistor (FDFET) will be described with reference to FIG. 1. Fully depleted field effect transistors are formed using a semiconductor-on-insulator (SOI) structure, wherein the semiconductor layer provided on the insulator layer has a smaller thickness than a channel depletion width. Thus, the electric charge and, accordingly, the body potential of the field effect transistor is fixed, which may be helpful for avoiding or at least reducing the floating body effect and for improving channel controllability. FIG. 1 shows a schematic cross-sectional view of a semiconductor device 100. The semiconductor structure includes a substrate 101. On the substrate 101, an electrically insulating layer 102 is formed. A semiconductor layer 103 is formed on the electrically insulating layer 102. The substrate 101, the electrically insulating layer 102 and the semiconductor layer 103 provide a semiconductor-on-insulator structure.
An isolation structure 104, for example, a shallow trench isolation structure, separates a portion of the semiconductor layer 103 wherein an active region of a fully depleted field effect transistor 105 is formed from other portions of the semiconductor layer 103 (not shown). On the semiconductor layer 103, a gate structure 106 is provided. The gate structure 106 includes a gate insulation layer 107, which may include a high-k material having a greater dielectric constant than SiO2, for example, Hf, and a gate electrode 110 including a metal portion 108 and a polysilicon portion 109. Adjacent the gate electrode 110, a sidewall spacer 112 is provided, which is separated from the gate electrode 110 by a liner layer 111. The field effect transistor 105 further includes a source region 114 and a drain region 116 adjacent the gate structure 106. The source region 114 and the drain region 116 are differently doped than a channel region 115 below the gate electrode 110, and may include source and drain extensions extending below the sidewall spacer 112. These features may be formed using techniques for providing a semiconductor-on-insulator structure, including oxidation, bonding, cleaving and polishing of semiconductor wafers, and techniques for forming field effect transistors, such as deposition, oxidation, photolithography, etching and ion implantation.
In particular, the semiconductor device 100 shown in FIG. 1 includes a metal gate portion 108 that may include one or more metal-containing layers. The metal gate portion 108 includes a work function adjusting material, for example, TiN. It is known that the effective work function of the metal gate portion 108 can be adjusted by added impurities, for example.
However, in the art, the problem arises that the effective work function of the metal gate on high-k dielectric significantly decreases after high temperature anneal carried out for activation of the source/drain implants and re-crystallization of the semiconductor layer 103 in order to heal defects caused by the ion implantation resulting in the generation of the source and drain regions 114 and 116. In particular, fabricating metal gate—metal oxide—semiconductor transistor devices with low threshold voltages poses severe problems due to oxygen vacancies and defect sites in the high-k gate dielectrics, causing Fermi level pinning phenomena that severely affect the overall performance of the devices.
In view of the above, the present invention provides techniques for adjusting the work function of a metal gate wherein the above-described problems are efficiently mitigated.